IMEC, the most advanced research firm in the world engaged in the study of semiconductors, recently shared its road map of the production of silicon and transistors of the sub-1 Nm at the Future Summit event in Antwerp, Belgium. The roadmap gives us an approximate idea of ​​the terms of up to 2036 for the following main technological nodes and transistor architectures that the company will explore and develop in its laboratories in cooperation with industry giants such as TSMC, Intel, Samsung and ASML.

The roadmap includes breakthrough structures of transistors, which develop from standard FINFET transistors, which will operate up to 3 nm, to new Gate All Around (GAA) nanostructures and 2 Nm and A7 (seven Angstrom) structures, respectively, followed by breakthroughs Structures such as CFET and atomic channels on A5 and A2. We remind you that ten Angstroms are 1 nm, so the IMEC roadmap covers the technological nodes less than “1 Nm”.

Perhaps you have not heard about the Mesuuni -Betray Center of microelectronics (IMEC), but it is one of the most important companies in the world along with better well -known companies such as TSMC and EUV ASML tools manufacturer. Although IMEC, focused on semiconductors, does not work with great famous, it serves the cornerstone of the semiconductor industry, combining such fierce competitors as Intel, TSMC and Samsung, with manufacturers of instruments for microcircuits such as ASML and Applied Materials, not to mention Already about no less important software development companies for semiconductors (EDA), such as Cadence and Synopsys, in an uncompetitive environment. This cooperation allows companies to determine the next generation of tools and software that they will use to develop and produce chips.

The standardized approach is becoming more and more important in the face of sharply increasing complexity and cost of development of microcircuits and tools for their manufacture. IMEC also collaborates with clients such as Intel or TSMC, for research and development of new technologies that they can use in their latest processors. The company is also known for helping pioneers in the field of EUV technology together with its long -standing ASML partner.

In the end, all advanced manufacturers of microcircuits use most of the same equipment obtained from several critical tool manufacturers, therefore, a certain level of standardization is needed. However, this requires efforts in the field of R&D, which can begin ten years before deployment, which means that IMEC roadmaps can give us a much longer idea of ​​the upcoming achievements in the semiconductor industry than short -term products of products from such companies as AMD, Intel and NVIDIA. In fact, many of these products would be simply impossible without the joint work of IMEC, undertaken by years before. Let's take a closer look at the roadmap and some additional technologies underly it.

The industry is faced with growing problems as technology develops, rapid growth in costs and nonlinear growth of demand for greater computing power, especially for machine learning.

IMEC is fully convinced that the Law of Moore is still alive and will live 52 years after it was written, although we believe that this does not apply to the economic component of the law, which also determined the lower cost of the transistor over time. In fact, as shown above, the costs of designing microcircuits are growing rapidly due to more complex design rules and longer design cycles, which helps to increase the cost of the transistor. In addition, a single-circuit increase in performance slows down from the turbulent days of 50% annual growth in the late 90s and early 2000s to ~ 5% per year.

However, if we do not take into account the density or economy, the Moore law usually remains in force with doubling the number of transistors every two years - the Apple M1 Ultra with 114 billion transistors even exceeds this watermark. In order to compensate for a decrease in the performance of single -flow calculations, we have witnessed the appearance of specialized computing devices (specialized processors designed for a narrow set of tasks), such as graphic processors. These devices are usually strongly parallel, which allows you to increase power/performance and efficiency of using the area at a faster pace.

IMEC notes that although earlier the need for greater computing power was doubled every two years, mainly in accordance with the increase in performance ensured by compliance with the Law of Moore, the raw computing power necessary for machine learning/AI is doubled by approximately every six months. This is an unpleasant problem, since even the ongoing doubling of the number of transistors will not be able to keep up with the pace. IMEC believes that a tripartite solution of size scale (including the better density and packaging technology), new materials and architecture of devices, as well as joint optimization of systemic technologies (SCTO) can keep the industry in the right line.

The first step is to enable the next generation tools. Today's 4th generation lithographic machines have 0.33 aperture, so chip manufacturers will have to use multipetterns (more than one exposure on the layer) to create the smallest elements for 2 nm and higher. Since the plate will have to be “printed” twice for one layer, the likelihood of defects is higher. This will lead to a decrease in performance and increase in the cycle (production) time, which will lead to an increase in costs.

Models with a high numerical aperture of the next generation (5th generation) will have an aperture of 0.55. This higher level of accuracy will create even smaller structures in one exposition, which will reduce the complexity of the design and improve performance, cycle time (more than 200 plates per hour) and cost. IMEC and ASML expect these tools will be available for mass production in 2026. The first tool with a high numerical aperture worth 400 million US dollars will be completed in ASML in the first half of 2023. IMEC will work in a test laboratory at the ASML facility to speed up access to the machine for chip manufacturers, first of all (ASML usually sends the tool to the IMEC plant).

Intel will be the first company to receive Twinscan Exe: 5200 with a high numerical Aperture for EUV, the supply of which is officially planned for 2025.

The second slide in the above gallery shows a roadmap for new types of transistors, which will ensure further fabrication of density and, I hope, some improvement in performance. Gate All Around (GAA)/Nanosheet transistors are debuted in 2024 with a 2-nm knot, replacing Finfet, which are used in modern advanced chips. We have already seen the announcements of several manufacturers of microcircuits, such as Intel Ribbonfet with four sheets that include various options for this transistor technology.

We remind you that ten Angstremov (a) are equal to one 1 nm. This means that A14 is 1.4 nm, A10 - 1 Nm, and we go to the era of less than 1 nm in 2030 with A7. Nevertheless, the agreement on the name of the process nodes turned more into a marketing exercise for chip markers than to a metric tied to any physical dimension. In the real world, the economy and performance of the technological process is affected by many factors, such as the density of transistors, peak performance, productivity on watts, various types of logic/circuits, density SRAM, and so on. In its diagrams, IMEC uses a step of metal and polymer in combination with standard names to provide several other important indicators. We can also see measurements of the density of transistors on the ASML slide (penultimate slide).

IMEC expects the GAA/Nanosheet and Forksheet transistors (at the most basic level, a denser GAA version) will last to the A7 node. Additional field transistors (CFET) will further reduce the area occupied when they appear around 2032, which will allow the use of more tightly packed libraries of standard cells. In the end, we will see versions of CFET with atomic channels that will further increase performance and scalability.

As you can see at the last two slides (presented by ASML at the event), the standard DUV led us to 100 mtr/mm^2 (megatransistor per square millimeter, density measurement), while today's numerical aperture 0.33 will contribute to the development of the industry . up to ~ 500 mr/mm^2. Future machines with a high numerical aperture will be required on the 2-nm process of process to bring it to ~ 1000 MTR/mm ^ 2 and, possibly, more with multipatttern.

Source: Tom's Hardware

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